A ring oscillator typically comprises a number of inverters connected in series as a ring. The inherent delays within each inverter cause the ring oscillator to oscillate in proportion to the total gate delay of the inverters in the ring.
FIG. 1 shows a typical ring oscillator 100 comprising an odd number of inverters 110. A tunable current source 101 may be provided to adjust the delay within each inverter 110, generally varying the oscillation frequency. One feature inherent in ring oscillator designs is that multiple phases of oscillation may be obtained at outputs 102-104 of inverters 110. Each of the inverters in FIGS. 1 and 2 are typically formed of CMOS transistors.
Existing voltage controlled oscillators (VCOs) use a variable capacitor or a current controlled source to control, adjust or influence the delay. The delay of each inverter is generally dependent upon the control input voltage in addition to the current provided by current source 101. Existing VCOs therefore generally require exacting attention to operating conditions and/or startup circuits.
VCOs with low gain tend to be more stable than VCOs with high gain. At high gain the voltage potential of the oscillation signal may reach levels that can introduce non-linearities to one or more components of the system. High gain VCOs therefore generally must adjust for process parameters to retain a nearly linear gain slope in the frequency vs. voltage curve (MHz/V). This can be challenging to implement. Therefore it is generally desirable to limit the gain of the oscillator.
Furthermore, in phase-locked loop (PLL) applications, it is useful to limit the frequency of oscillation and to keep the circuit within the capabilities of the phase detector/phase frequency detector (PD/PFD) and the locking circuitry. Also, in some cases limiting the maximum frequency can help to prevent runaway (i.e., a condition where the loop cannot lock and the frequency continually increases until the system fails.)
Thus it is desirable to have a relatively stable voltage controlled oscillator that demonstrates a high tolerance to variable and/or varying component values (e.g., process corners), and which imposes an upper bound on the output frequency.